Many electronic circuits require a relatively constant voltage source to operate properly. Such circuits are typically powered by an energy source such as main power or a battery. Unfortunately, the output voltage of these energy sources may fluctuate substantially. Therefore, the electronics art has developed various regulator circuits that convert the voltage of the energy source to a relatively constant voltage for use by other circuits.
Several aspects of a voltage regulator may limit its effectiveness in a particular circuit. For example, some regulators have a high "drop out" voltage. Drop-out voltage is the minimum voltage difference between the input and output voltages of the regulator necessary to maintain output regulation. Other regulators are only stable for a narrow range of load impedances. Some regulators also go out of regulation when the load goes into an idle state that requires an insignificant quantity of current. Voltage regulators typically use negative feedback to maintain a substantially constant output voltage despite significant fluctuations in the energy source and load. One type of regulator using negative feedback is a linear regulator. A linear regulator may, for example, include a dissipative element such as an NPN bipolar junction transistor that is controlled by an amplifier coupled to the base of the transistor in a negative feedback loop. The transistor thus imposes a variable voltage drop between the input and output of the regulator. The voltage at the regulator output can be controlled by adjusting the conductance of the transistor. It is noted that other dissipative elements may be substituted for the NPN transistor.
This type of linear regulator typically has a significant problem in that it has a high drop-out voltage which limits the minimum input voltage that may be accepted by the circuit. The drop-out voltage of the linear regulator is caused by the cumulative effect of two factors. First, the potential at the base of the transistor is greater than the potential at the output of the regulator by approximately one diode voltage drop across the base-emitter junction of the transistor. Second, the amplifier must be capable of establishing the voltage at the base of the transistor to establish this diode voltage drop. These two factors combine to represent a drop-out voltage of at least one volt, and perhaps as much as two volts in regulators using a Darlington pair, because the amplifier is typically powered by the input to the regulator. When the regulator is provided with insufficient input voltage, its output voltage drops out of regulation. A regulator of this type may thus have a drop-out voltage on the order of one to two volts.
A large drop-out voltage has several bad effects. First, as discussed above, the drop-out voltage limits the minimum input voltage which can be used with the regulator. Additionally, the drop-out voltage represents wasted power. Furthermore, the power dissipated by the regulator is turned into heat, which must be dissipated by a heat sink or fan.
Heretofore known regulators have been developed to provide a low drop-out voltage (hereinafter "LDO regulator"). An LDO regulator typically uses a lateral PNP bipolar junction transistor as an output device. An amplifier is coupled to the base of the PNP transistor in a negative feedback loop for controlling the output voltage at the collector of the PNP transistor. A reference voltage is applied to another input of the amplifier. Negative feedback allows the regulator to maintain a substantially constant output voltage at the collector of the PNP transistor. If the output voltage decreases slightly, the output of the amplifier reduces the voltage across the base-emitter junction of the PNP transistor which causes the transistor to conduct more current and thus brings the output voltage back up to the desired voltage.
The PNP LDO regulator provides for a low drop-out voltage because the drop-out of the PNP transistor is limited only by its inherent saturation voltage plus any ohmic losses in the emitter and collector of the transistor. This type of device may provide a drop-out voltage at full current of less than one-half a volt.
LDO regulators that use PNP output transistors also have several problems. First, the open-loop output impedance of the PNP LDO regulator is relatively large. The high open-loop output impedance leads to stringent stability requirements which limit the range of load impedances that may properly operate from the output of the regulator. Negative feedback is used to achieve a low closed loop output impedance for the voltage regulator. As described above, the feedback loop adjusts the voltage of the base of the PNP transistor so as to oppose any change in output voltage. If the loop is not properly compensated, the output voltage will become unstable and will oscillate. The requirements of loop compensation thus limit the range of load impedances which may be used with the PNP LDO regulator. Finally, the operating performance of the PNP transistor is inferior to the operating performance of the NPN transistor.
The stability of a PNP LDO regulator is determined by the frequency associated with two poles of the system. First, the load that is coupled to the LDO regulator introduces a pole into the system (the "load pole"). The load pole is caused by the combination of the capacitance and the resistance of the load itself. Therefore, the location of this pole is not controlled by the design of the LDO. Unfortunately, this pole is not stationary. In fact, the frequency of the pole changes with the operation of the load. The second pole is caused by a parasitic capacitance at the base of the PNP transistor in combination with the output resistance of the amplifier (the "parasitic pole"). Due to the size of the parasitic capacitance of the PNP transistor, the parasitic pole is located at a low frequency and may be within the audio range. Therefore, the LDO regulator coupled to a load may be approximated as a two pole system resulting in a 180.degree. phase shift. This phase shift reduces the system's phase margin and the system may thus begin to oscillate depending on the location of the load pole. A typical solution is to utilize the equivalent series resistance (ESR) of a capacitor at the output of the LDO to introduce a zero into the system to compensate for one of the poles. However, the addition of an ESR zero does not entirely eliminate the stability problem because the load pole still depends on the load impedance, and the ESR zero may not be able to stabilize the regulator for all load impedances.
The PNP transistor itself limits the usefulness of a PNP LDO. First, the high-current beta of a PNP transistor is very limited in comparison to the high-current beta of a comparable NPN transistor. Additionally, the base current causes poor efficiency because current is taken from the emitter and passed through the base to ground resulting in an efficiency loss. Finally, a lateral PNP transistor exhibits substrate injection in saturation which results in a loss of current and efficiency.
A PMOS transistor may be used in place of the PNP transistor to reduce or eliminate several problems of the PNP described above. For example, the PMOS transistor does not experience the high-current beta limitation of the PNP counterpart nor the efficiency loss due to base current. Rather, the PMOS transistor merely conducts current between source and drain without any appreciable current loss at its gate. Additionally, the PMOS LDO regulator does not experience substrate injection. However, the PMOS LDO regulator does not improve the stability over PNP LDO regulators.
Some circuit designers have tried to cure the stability problem with a CMOS solution by using an NMOS follower as the output stage of the amplifier that controls the PMOS transistor. Such circuits have not adequately addressed the stability problem. In fact, the design of these CMOS circuits introduces significant design problems in setting the threshold voltage of the transistors in the NMOS follower. If the threshold voltage of the. NMOS follower is set at a relatively low absolute value so that the PMOS output transistor may be turned off, the NMOS transistor cannot be turned off. If the threshold voltage of the NMOS follower is set high, then the absolute value of the PMOS output transistor's threshold voltage must be proportionately increased, reducing the available gate drive and requiring an increase in transistor size.